Isolation in integrated circuit devices

ABSTRACT

Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation (and claims benefit of priority under35 U.S.C. § 120) of U.S. application Ser. No. 16/483,641, filed Aug. 5,2019, entitled “ISOLATION IN INTEGRATED CIRCUIT DEVICES,” which is a 371of PCT International Application No. PCT/US2017/020842, filed Mar. 5,2017, entitled “ISOLATION IN INTEGRATED CIRCUIT DEVICES.” The disclosureof each prior application is considered part of (and is incorporated byreference in) the disclosure of this application.

BACKGROUND

Integrated circuit (IC) devices typically include various structures(e.g., electrically conductive or semi-conductive structures) insulatedfrom each other by a dielectric material. In some fabricationtechniques, the structures are first formed, and the dielectric materialis then deposited over and/or around the structures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. To facilitatethis description, like reference numerals designate like structuralelements. Embodiments are illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings.

FIGS. 1-4 are cross-sectional views of various stages in the manufactureof an integrated circuit (IC) device using a protective layer technique,in accordance with various embodiments.

FIGS. 5-8 are cross-sectional views of various stages in the formationand isolation of semiconductor fins of an IC device using the protectivelayer technique of FIGS. 1-4, in accordance with various embodiments.

FIGS. 9A-9D and 10A-10D are views of various stages in the formation andisolation of gates in a tri-gate transistor using the protective layertechnique of FIGS. 1-4, in accordance with various embodiments.

FIGS. 11A-11D and 12A-12D are views of various stages in the formationand isolation of gates in an all-around gate transistor using theprotective layer technique of FIGS. 1-4, in accordance with variousembodiments.

FIG. 13 is a flow diagram of a process for providing a dielectric layer,in accordance with various embodiments.

FIGS. 14A and 14B are top views of a wafer and dies that may includedielectric layers formed using any of the protective layer techniquesdisclosed herein.

FIG. 15 is a cross-sectional side view of an IC device that may includedielectric layers formed using any of the protective layer techniquesdisclosed herein.

FIG. 16 is a cross-sectional side view of an IC device assembly that mayinclude dielectric layers formed using any of the protective layertechniques disclosed herein.

FIG. 17 is a block diagram of an example computing device that mayinclude dielectric layers formed using any of the protective layertechniques disclosed herein.

DETAILED DESCRIPTION

Disclosed herein are techniques for providing isolation in integratedcircuit (IC) devices, as well as IC devices and computing systems thatutilize such techniques. In some embodiments, a protective layer may bedisposed on a structure in an IC device, prior to deposition ofadditional dielectric material, and the resulting assembly may betreated to form a dielectric layer around the structure.

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, wherein like numeralsdesignate like parts throughout, and in which is shown, by way ofillustration, embodiments that may be practiced. It is to be understoodthat other embodiments may be utilized and structural or logical changesmay be made without departing from the scope of the present disclosure.Therefore, the following detailed description is not to be taken in alimiting sense.

Various operations may be described as multiple discrete actions oroperations in turn, in a manner that is most helpful in understandingthe disclosed subject matter. However, the order of description shouldnot be construed as to imply that these operations are necessarily orderdependent. In particular, these operations may not be performed in theorder of presentation. Operations described may be performed in adifferent order from the described embodiment. Various additionaloperations may be performed, and/or described operations may be omittedin additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B”means (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B, and C). The term “between,” when usedwith reference to measurement ranges, is inclusive of the ends of themeasurement ranges. As used herein, a “high-k dielectric material” mayrefer to a material having a higher dielectric constant than siliconoxide.

The description uses the phrases “in an embodiment” or “in embodiments,”which may each refer to one or more of the same or differentembodiments. Furthermore, the terms “comprising,” “including,” “having,”and the like, as used with respect to embodiments of the presentdisclosure, are synonymous. The disclosure may use perspective-baseddescriptions such as “above,” “below,” “top,” “bottom,” and “side”; suchdescriptions are used to facilitate the discussion and are not intendedto restrict the application of disclosed embodiments.

The accompanying drawings are not necessarily drawn to scale. While somefigures generally indicate straight lines, right angles, and smoothsurfaces, an actual implementation of the disclosed techniques may haveless than perfect straight lines, right angles, etc., and some featuresmay have surface topology or otherwise be non-smooth, given the realworld limitations of fabrication processes. For ease of exposition, theterm “FIG. 9” may be used to refer to the collection of FIGS. 9A-9D, theterm “FIG. 10” may be used to refer to the collection of FIGS. 10A-10D,the term “FIG. 11” may be used to refer to the collection of FIGS.11A-11D, the term “FIG. 12” may be used to refer to the collection ofFIGS. 12A-12D, and the term “FIG. 14” may be used to refer to thecollection of FIGS. 14A-14B.

As the dimensions of integrated circuit (IC) devices shrink,conventional dielectric deposition techniques may be unable toadequately fill the high aspect ratio trenches between close-togetherstructures. For example, existing dielectric deposition processes suchas sub-atmospheric CVD (SACVD), low-pressure CVD (LPCVD),plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), andspin-on deposition (SOD) can have issues with seams/voids, surfacesensitivity, adhesion issues, and shrinkage issues, all of which mayaffect performance. Newer techniques, such as flowable chemical vapordeposition (FCVD) may overcome some of these issues, but may causedegradation of the adjacent structures. When the adjacent structures arethin, this degradation may substantially compromise the integrity of theIC device, resulting in mechanical or electrical failure (e.g., bybending or collapsing). Thus, the design of IC devices mustconventionally include features that are wide or large enough towithstand this damage, limiting the degree to which narrow or highaspect ratio features can be included in a manufacturable device.

Disclosed herein are protective layer techniques for dielectricdeposition. These protective layer techniques may mitigate thedegradation caused by aggressive dielectric deposition, and thus mayimprove the reliability and integrity of the resulting IC devices. Theprotective layer techniques disclosed herein may be used at any suitablestage(s) in IC fabrication. For example, the protective layer techniquesdisclosed herein may be useful whenever an underlying structure issusceptible to degradation due to the subsequent deposition of adielectric material. The protective layer techniques disclosed hereinmay be particularly useful in such settings when the underlyingstructure includes narrow features that may be structurally orelectrically compromised by this degradation. FIGS. 1-4 discuss variousembodiments of the protective layer techniques with reference to generalstructures, and further figures illustrate some particular, non-limitingsettings in which the protective layer techniques of FIGS. 1-4 may beusefully applied.

FIGS. 1-4 illustrate various stages in an integrated circuit (IC) devicefabrication process flow, in accordance with various embodiments. FIG. 1is a cross-sectional view of an assembly 200 including a base 102 andone or more structures 108 disposed thereon. The base 102 may includeany underlying material or materials on which the structures 108 aredisposed; for example, as discussed below, the base 102 may be asemiconductor substrate (e.g., a wafer), a silicon-on-insulator (SOI)structure, a fin structure, an interlayer dielectric stack includingactive and/or passive devices, etc. The structures 108 may includesemiconductor material, dielectric material, conductive material, or anyother suitable material arranged as desired. Although the structures 108are illustrated as substantially rectangular in cross-section, this issimply for ease of illustration, and the structures 108 may have anysuitable shape.

The structures 108 may have any suitable dimensions. In someembodiments, the structures 108 may be “narrow” in the sense that thestructures 108 have a small width 107. In some embodiments, the width107 of a structure 108 may be less than 5 nanometers (e.g., less than 4nanometers, between 2 nanometers and 5 nanometers, between 3 nanometersand 5 nanometers, or between 3 nanometers and 4 nanometers). In someembodiments, the width 107 may be between 3 nanometers and 8 nanometers.In some embodiments, the structures 108 may have a height 109 between100 nanometers and 200 nanometers (e.g., between 125 nanometers and 145nanometers, between 145 nanometers and 165 nanometers, between 165nanometers and 185 nanometers, or any other range).

The structures 108 may be spaced apart by recesses 106. In someembodiments, the structures 108 may be formed by patterning the recesses106 into an initial base 102, while in other embodiments, the structures108 may be fabricated by depositing additional materials onto the base102. In some embodiments, adjacent structures 108 may be “close”together in that the recess 106 between them has a small width 103. Insome embodiments, the width 103 may be less than or equal to 50nanometers (e.g., less than or equal to 10 nanometers, less than orequal to 20 nanometers, less than or equal to 30 nanometers, or lessthan or equal to 40 nanometers). In some embodiments, a recess 106 mayhave a width 103 between 5 nanometers and 50 nanometers.

The height 109 of the structures 108 may also be considered to be theheight 109 of the recesses 106. In some embodiments, a recess 106 mayhave a height-to-width aspect ratio (i.e., a ratio of the height 109 tothe width 103, also referred to herein as an “aspect ratio”) between 1:1and 50:1 (e.g., between 10:1 and 40:1, between 10:1 and 20:1, between5:1 and 10:1, between 10:1 and 15:1, equal to 25:1, equal to 30:1, equalto 35:1, equal to 40:1, or equal to 45:1). In some embodiments, therecess 106 may have a height-to-width aspect ratio greater than 3:1,greater than 4:1, greater than 7:1, greater than 8:1, or greater than10:1.

FIG. 2 illustrates an assembly 202 subsequent to providing a protectivelayer 105 on the assembly 200 (FIG. 1). The protective layer 105 may bea conformal layer, covering the sidewalls and top of the structures 108and the bottoms of the recesses 106. In some embodiments, the protectivelayer 105 may be provided by atomic layer deposition (ALD) or LPCVD.

The protective layer 105 may have any suitable material composition, andthe particular material composition may depend on the choice of initialdielectric material 111, as discussed below. In some embodiments, theprotective layer 105 may include silicon, silicon oxide, siliconnitride, silicon carbide, silicon oxynitride, other oxides, othernitrides, other carbides, or any suitable combination of materials. Thematerial composition of the protective layer 105 may be selected toachieve a desired level of “hermeticity” to the initial dielectricmaterial 111; that is, the material composition of the protective layer105 may serve as an adequate barrier to limit degradation of thestructures 108 by the initial dielectric material 111.

In some embodiments, the protective layer 105 may be strained so as toexert a force on the underlying structures 108, and thereby alter theelectrical properties of the underlying structures 108 (e.g., alteringthe conductivity, as known in the art). The amount of tensile orcompressive strain in the protective layer 105 may be tuned byappropriately selecting the time, temperature, deposition conformality,and environmental conditions of deposition of the protective layer 105,as known in the art. The protective layer 105 may have any suitablethickness, which may depend on the deposition conditions of theprotective layer 105 and its desired electrical properties. For example,in some embodiments, the thickness of the protective layer 105 may bebetween 1 nanometer and 4 nanometers.

FIG. 3 illustrates an assembly 204 subsequent to providing an initialdielectric material 111 on the assembly 202 (FIG. 2). The initialdielectric material 111 may be spaced apart from the structures 108 bythe intervening protective layer 105. The initial dielectric material111 may be disposed within the one or more recesses 106 and may bedisposed over the upper surfaces of the structures 108, as desired. Insome cases, it may be desirable to provide a sufficient amount of theinitial dielectric material 111 so as to provide a sufficient overburdenof the initial dielectric material 111 over the structures 108 forsubsequent processing (e.g., planarization and/or recessing, asdiscussed below with reference to FIGS. 7-8, 10, and 12). The variousprocess conditions of the provision of the initial dielectric material111 (e.g., pressure, temperature, chemical composition of ambientenvironment, etc.) may be customized as desired for particular targetapplication or end-use.

Any suitable technique may be used to provide the initial dielectricmaterial 111. In some embodiments, the initial dielectric material 111may be deposited using a flowable chemical vapor deposition (FCVD)process, then cured and/or annealed. In some such embodiments, theselected FCVD process may utilize remote plasma-enhanced CVD (RPECVD).Using such a remote plasma process may help to maintain a low processingtemperature, which in turn may help to maintain a desiredfluidity/flowability of the initial dielectric material 111.

In some embodiments, the provision of the initial dielectric material111 may begin with a flow of a silazane (SiH₂NH)_(n)-based polymer witha silicon-based precursor, such as trisilylamine (N(SiH₃)₃). Thisexample should not be taken as limiting, however; the individualprecursor(s) and reactive gas(es) of the initial dielectric material111, as well as their ratio, can be customized as desired for a giventarget application or end-use. In some embodiments, the initialdielectric material 111 may include any dielectric material that is (1)flowable (e.g., compatible with deposition using an FCVD process),and/or (2) suitable for deposition within recesses 106 of relativelyhigh aspect ratio (e.g., having an aspect ratio in the range of about3:1 to 40:1, in some cases).

In some embodiments, the curing of the initial dielectric material 111may include providing an ambient environment of ozone (O₃), oxygen (O₂),and/or other initiation oxidant. In some embodiments, the curing of theinitial dielectric material 111 may be performed under a flow of O₃having a flow rate, for example, in the range of about 2.0×10⁴-5.4×10⁴standard cubic centimeters per minute (sccm). In some embodiments, thecuring of the initial dielectric material 111 may be performed under aflow of O₂ having a flow rate, for example, in the range of about2.5×10³-5.0×10³ sccm. In some cases, curing of the initial dielectricmaterial 111 may be performed at a temperature, for example, in therange of about 120-180 degrees C. (e.g., between 145 and 155 degrees C.,or any other sub-range in the range of 120-180 degrees C.). In somecases, curing of the initial dielectric material 111 may be performed ata pressure, for example, in the range of about 500-700 Torr (e.g.,between 550 and 650 Torr, or any other sub-range in the range of 500-700Torr).

In some cases, curing the initial dielectric material 111 in anoxidant-rich environment may help to reduce silicon-nitrogen (Si—N)bonds and/or silicon-hydrogen (Si—H) bonds present after deposition ofthe initial dielectric material 111. That is, in some instances, thepresence of silicon-hydrogen (Si—H) bonds may be decreased significantly(e.g., due to their relatively lower bond energy in an O₃-based curingtreatment) and silicon-oxygen (Si—O) bond intensity may increasesignificantly and come to replace the silicon-nitrogen (Si—N) bondsinitially present in the initial dielectric material 111. Thus, in somecases, the initial dielectric material 111 may become a stable oxide,such as silicon dioxide (SiO₂, or silica). In some other instances, theinitial dielectric material 111 may become a stable nitride, such assilicon nitride (Si₃N₄). In some still other instances, the initialdielectric material 111 may become a stable carbide.

In some embodiments, the initial dielectric material 111 may undergo awet chemical treatment process. In some cases, wet chemical treatmentmay be performed, for instance, using a wet bench process which utilizeshot de-ionized water (HDIW). In some other cases, wet chemical treatmentmay be performed, for instance, using a single wafer wet process whichutilizes de-ionized water (DIW) at a temperature in the range of about40-80 degrees C. (e.g., between 45 and 60 degrees C., or any othersub-range in the range of about 40-80 degrees C.). In some otherembodiments, wet chemical treatment may be performed, for instance,using a single wafer wet process which utilizes a standard SC-1chemistry utilizing at least one of ammonium hydroxide (NH₄OH), hydrogenperoxide (H₂O₂), hot de-ionized water (HDIW), and/or de-ionized water(DIW) at a temperature, for example, in the range of about 50-100degrees C. (e.g., about 60-80 degrees C., or any other sub-range in therange of about 50-100 degrees C.). In some such cases, the flow rate ofammonium hydroxide (NH₄OH) may be in the range of about 30-200milliliters per minute (mL/min) (e.g., in the range of 120-130 mL/min,or any other sub-range in the range of about 30-200 mL/min). The flowrate of hydrogen peroxide (H₂O₂) may be, in some cases, in the range ofabout 100-400 mL/min (e.g., in the range of 230-260 mL/min, or any othersub-range in the range of about 100-400 mL/min). The flow rate of hotde-ionized water (HDIW) may be, in some cases, in the range of about1,500-1,800 mL/min (e.g., in the range of 1,600-1,650 mL/min, or anyother sub-range in the range of about 1,500-1,800 mL/min). The flow rateof de-ionized water (DIW) may be, in some cases, in the range of about300-400 mL/min (e.g., in the range of 350-375 mL/min, or any othersub-range in the range of about 300-400 mL/min). Other processconditions or techniques for in-situ curing of the initial dielectricmaterial 111 may be used as suitable.

FIG. 4 illustrates an assembly 206 subsequent to performing apost-treatment on the assembly 204 (FIG. 3) to convert the protectivelayer 105 and the initial dielectric material 111 into a dielectriclayer 110. In some embodiments, this conversion may occur when thepost-treatment environment causes components of the initial dielectricmaterial 111 to diffuse into the protective layer 105 and homogenize thematerial composition of the protective layer 105 and the initialdielectric material 111. For example, one or more oxidants included inthe initial dielectric material 111 may diffuse into the protectivelayer 105 as a result of an oxidant-rich post-treatment environment(e.g., combined with a high temperature, such as a temperature between300 and 800 degrees Celsius), converting the protective layer 105 andthe initial dielectric material 110 into a relatively homogenousdielectric layer 110.

In some embodiments, the dielectric layer 110 may be an oxide-baseddielectric layer, a nitride-based dielectric layer, and/or acarbide-based dielectric layer. The various process conditions of thepost-treatment (e.g., pressure, temperature, chemical composition ofambient environment, intensity, power, bias, process time, etc.) may becustomized as desired for a given target application or end-use. In someembodiments, post-treatments may, in addition to converting theprotective layer 105 and the initial dielectric material 111 into asubstantially homogeneous dielectric layer 110, (1) eliminate orotherwise reduce the presence of seams/voids within the dielectric layer110; (2) eliminate or otherwise reduce the presence of impurities withinthe dielectric layer 110; (3) modify the dielectric properties of thedielectric layer 110; (4) modify the etch rate of the dielectric layer110; and/or (5) increase the density of the dielectric layer 110.

In some embodiments, the cured initial dielectric material 111 and theprotective layer 105 may undergo a thermal treatment process as part offorming the dielectric layer 110. Thermal treatment can be performedusing any of a wide range of techniques, such as furnace annealing,rapid thermal annealing, flash annealing, ultraviolet (UV) light-basedoxidation, electron beam annealing, and/or a combination of any one ormore thereof. In some cases, a furnace-based, vertical directionalsolidification (VDS) process may be utilized, in which, within anenvironment of about 90% steam or greater (in some embodiments), theassembly 204 is subjected to a temperature between 400 and 800 degreesCelsius for a time between 1 and 10 hours. In some embodiments, thethermal treatment of the dielectric layer 110 may help, for example, toremove impurities, such as silicon-hydroxide (Si—OH) bonds and/or water(H₂O), which may be present in the dielectric layer 110. Other suitabletechniques for thermal treatment of the assembly 204 will depend on agiven application and will be apparent in light of this disclosure. Insome embodiments, a thermal treatment may be combined with othertreatment conditions, such as pressure and environmental chemistry, toachieve a desired result. For example, a diffusion treatment may includeperforming a thermal treatment at a suitable pressure and with suitablechemical species in the environment of the assembly 204.

In some embodiments, the cured initial dielectric material 111 and theprotective layer 105 may undergo a plasma treatment process as part offorming the dielectric layer 110. Plasma treatment can be performed, forexample, using a high-density and/or low-density plasma annealingprocess. In some cases, plasma treatment may be performed using an inertgas-based plasma, for example, with high power, low bias, and atemperature in the range of about 350-550 degrees C. (e.g., about400-525 degrees C., or any other sub-range in the range of about 350-550degrees C.). In some embodiments, the inert gas may include helium.However, the material composition, power, bias, and/or temperatureutilized in the selected plasma treatment(s) can be customized asdesired for a given target application or end-use.

As noted above, in some embodiments, the post-treatment may serve, atleast in part, to modify the dielectric properties of the dielectriclayer 110. For example, in some cases, the post-treatment may modify thedielectric layer 110 so as to bring its dielectric constant (K-value)into a desired range (e.g., in the range of 3.0-6.0, in the range of4.5-5.0, or in the range of 5.0-5.5).

In some cases, the post-treatment may serve, at least in part, todensify the dielectric layer 110. In some instances, this may help toensure that the resultant densified dielectric layer 110 can withstandsubsequent processing (e.g., etching, planarization, etc.). However, aswill be appreciated in light of this disclosure, it may be desirable toensure that the density of the dielectric layer 110 is not made soexcessive as to prevent or otherwise overly inhibit etching thereof.That is, in some instances, it may be desirable to ensure thatdielectric layer 110 is sufficiently resistant, for example, to wetetching (e.g., by a hydrofluoric, or HF, acid-based wet etch chemistry),to provide for desired etching thereof. In a more general sense, thedensity of the dielectric layer 110 can be customized as desired for agiven target application or end-use. Examples of further processingoperations that may be performed on the dielectric layer 110 arediscussed below (e.g., with reference to FIGS. 7, 8, 10, and 12)

As noted above, the protective layer techniques discussed herein may beapplied at any of a number of different stages in the fabrication of anIC device. FIGS. 5-8, FIGS. 9-10, and FIGS. 11-12 illustrate a number ofdifferent settings in which the protective layer techniques disclosedherein may be used.

FIGS. 5-8 are cross-sectional views of various stages in the manufactureof an IC device including fins 113, in accordance with some embodiments.In particular, FIGS. 5-8 illustrate an embodiment in which theprotective layer techniques disclosed herein are used to isolatedifferent ones of the fins 113 from each other. Use of a protectivelayer technique in the isolation of the fins 113 may limit the erosionto the fins 113 that may be caused by aggressive deposition techniques(e.g., FCVD), while retaining the gap-filling performance of thesedeposition techniques.

FIG. 5 illustrates an assembly 208 that is an embodiment of the assembly204 of FIG. 3; in the assembly 208, the structures 108 are provided byfins 113 and portions of hardmask 104 disposed thereon, and the base 102is provided by a semiconductor substrate 115. The recesses 106 may bedisposed between adjacent fins 113, and may extend down to thesemiconductor substrate 115. The protective layer 105 covers thestructures 108, and an initial dielectric material 111 is disposed onthe protective layer 105; the protective layer 105 and the initialdielectric material 111 may take the form of any of the embodimentsdisclosed herein. As known in the art, the fins 113 may be utilized, forexample, in forming fin-based transistor devices (e.g., the tri-gate andall-around gate transistor devices discussed below with reference toFIGS. 9-10 and FIGS. 11-12), and/or other suitable fin-basedsemiconductor architectures.

The semiconductor substrate 115 may be formed from any suitablesemiconductor material (or combination of such materials), such assilicon (Si), germanium (Ge), and/or silicon germanium (SiGe). In someembodiments, the semiconductor substrate 115 may be a bulk substrate, asilicon-on-insulator (SOI) structure, a wafer, and/or a multi-layeredstructure.

The hardmask 104 may include any suitable hardmask material (orcombination of such materials). For example, in some embodiments, thehardmask 104 may include a nitride, such as silicon nitride (Si₃N₄) ortitanium nitride (TiN); an oxide, such as silicon dioxide (SiO₂);silicon carbon nitride (SiCN); silicon oxynitride (SiO_(x)N_(y)); and/ora combination of any one or more thereof.

The hardmask 104 can be formed using any suitable technique (orcombination of techniques). For example, the hardmask 104 may be formedusing a chemical vapor deposition (CVD) process, a physical vapordeposition (PVD) (e.g., sputtering), electron beam evaporation, and/or acombination of any one or more thereof. The dimensions (e.g., thickness)of the hardmask 104 can be customized as desired for a given targetapplication or end-use. In some embodiments, the hardmask 104 may have asubstantially uniform thickness, while in other embodiments, thehardmask 104 may have a non-uniform or otherwise varying thickness

The hardmask 104 may be patterned using any suitable lithographytechnique (or combination of such techniques). As known in the art, thepattern of the hardmask 104 may be used to define the pattern of thefins 113, and thus the dimensions (e.g., width) of the openingspatterned into the hardmask 104 may contribute to determining the widths103 and 107 of the recesses 106 and fins 113, respectively. Note that,in the embodiment of FIGS. 5-8, the width 103 is the width of the recess106 at the “bottom” of the recess 106, and the width 107 is the width ofa fin 113 at the “top” of the fin 113. In some embodiments, the hardmask104 may be omitted from the assembly 208.

In some embodiments, the fins 113 may be formed by etching the recesses106 into an initial semiconductor substrate 115, in accordance with thepattern of the hardmask 104. The initial semiconductor substrate 115 maybe patterned using any suitable lithography technique (or combination ofsuch techniques), such as wet etch and/or dry etch processes followed bypolishing, cleans, etc., as known in the art. In some embodiments, theassembly 208 may be the product of highly directional (e.g.,anisotropic) dry etching in accordance with the pattern of the hardmask104, etching into the initial semiconductor substrate 114 and formingthe fins 113 and the one or more recesses 106.

The fins 113 and recesses 106 of the assembly 208 may have any suitabledimensions. In some embodiments, the width 107 of the fins 113 may beless than 5 nanometers (e.g., less than 4 nanometers, between 2nanometers and 5 nanometers, between 3 nanometers and 5 nanometers, orbetween 3 nanometers and 4 nanometers). In some embodiments, the width107 of the fins 113 may be between 3 nanometers and 8 nanometers. Insome embodiments, the fins 113 may have a height 109 between 100nanometers and 200 nanometers (e.g., between 125 nanometers and 145nanometers, between 145 nanometers and 165 nanometers, between 165nanometers and 185 nanometers, or any other range). In some embodiments,the width 103 of the recesses 106 may be less than or equal to 70nanometers (e.g., less than or equal to 10 nanometers, less than orequal to 20 nanometers, less than or equal to 30 nanometers, or lessthan or equal to 40 nanometers). In some embodiments, a recess 106 mayhave a width 103 between 5 nanometers and 50 nanometers. In someembodiments, a recess 106 may have an aspect ratio (i.e., a ratio of theheight 109 to the width 103) between 1:1 and 50:1 (e.g., between 10:1and 40:1, between 10:1 and 20:1, between 5:1 and 10:1, between 10:1 and15:1, equal to 25:1, equal to 30:1, equal to 35:1, equal to 40:1, orequal to 45:1). In some embodiments, the recess 106 may have aheight-to-width aspect ratio greater than 3:1, greater than 4:1, greaterthan 7:1, greater than 8:1, or greater than 10:1.

FIG. 6 illustrates an assembly 210 subsequent to processing theprotective layer 105 and the initial dielectric material 111 to form adielectric layer 110 over the fins 113 and the hardmask 104 of theassembly 208 (FIG. 5), in accordance with any of the techniquesdiscussed herein (e.g., with reference to FIGS. 3 and 4). The assembly210 of FIG. 6 is thus an embodiment of the assembly 206 of FIG. 4. Asillustrated in FIG. 6, the dielectric layer 110 may extend over the fins113 and the hardmask 104, and thus may be said to overburden theassembly 208. The dielectric layer 110 may fill or substantially fillthe recesses 106.

FIG. 7 illustrates an assembly 212 subsequent to planarizing theassembly 210 (FIG. 6) to remove material at the “top” surface of theassembly 210. The planarization may remove (1) excess portions of thedielectric layer 110; (2) the hardmask 104; and/or (3) excess portionsof the one or more fins 113. In some embodiments, the planarization mayinclude a chemical-mechanical planarization (CMP) process, anetch-and-clean process, and/or any other suitable planarization/polishprocess, as appropriate.

FIG. 8 illustrates an assembly 214 subsequent to recessing thedielectric layer 110 of the assembly 212 (FIG. 7). The dielectric layer110 may be recessed using any suitable technique (or combination oftechniques). For example, in some embodiments, the dielectric layer 110may be recessed using a chemical (e.g., remote plasma-based) dry etchprocess, or a hydrofluoric acid (HF) acid-based wet etch chemistry.Recessing the dielectric layer 110 may reduce its thickness, therebyexposing one or more portions 112 of the one or more fins 113. Theexposed portion 112 of a given fin 113 may be available for downstreamuse or further processing. For example, a given portion 112 may providea structure upon which an additional layer and/or components can bepopulated; for example, the portion 112 may provide the fin 344discussed below with reference to FIGS. 9-10, or the fin 354 discussedbelow with reference to FIGS. 11-12. Thus, recessing the dielectriclayer 110 may help to define the active fin area of active fin devicesformed from the assembly 214, and the dielectric layer 110 may provideisolation between active fin devices, in accordance with someembodiments.

FIGS. 9-10 are various views of example stages in the manufacture of anIC device including a tri-gate transistor, in accordance with variousembodiments. In particular, FIGS. 9-10 illustrate an embodiment in whichthe protective layer techniques disclosed herein are used to provide adielectric layer 110 around spacers 330 that abut the gate of a tri-gatetransistor. Aggressive dielectric deposition techniques may damage thespacers 330; use of the protective layer techniques disclosed herein maypreserve the spacers 330 during deposition of the dielectric layer 110.

FIG. 9A is a side cross-sectional view of an assembly 216 along the fin344, FIG. 9B is a cross-sectional view taken through the section A-A ofFIG. 9A, FIG. 9C is a side view taken toward the carrier reservoir 306,and FIG. 9D is a top view. The assembly 216 is an embodiment of theassembly 204 of FIG. 3; in the assembly 216, the structures 108 areprovided by gate material 366, a hardmask 337, and spacers 330 disposedat opposite faces of the gate material 366/hardmask 337. The base 102 isprovided by a fin 344 on and around which the gate material 366 and thespacers 330 are disposed. The protective layer 105 covers the structure108, and an initial dielectric material 111 is disposed on theprotective layer 105; the protective layer 105 and the initialdielectric material 111 may take the form of any of the embodimentsdisclosed herein.

The assembly 216 may include a substrate 302 on which carrier reservoirs306 and 307 are disposed. The carrier reservoirs 306 may provide thesource and drain for a tri-gate transistor formed from the assembly 216.In some embodiments, the carrier reservoirs 306 and 307 may be embeddedepi carrier reservoirs, and may be formed by epitaxy after the formationof the fin 344. For example, the carrier reservoirs 306 and 307 mayinclude an epitaxially grown single crystalline semiconductor such as,but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs,InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In other embodiments, thecarrier reservoirs 306 and 307 may be doped extensions of the fin 344.The carrier reservoirs 306 and 307 may have an n-type conductivity or ap-type conductivity. In some embodiments, the carrier reservoirs 306 and307 have a doping concentration between 3×10¹⁸ atoms/cm³ to 3×10²¹atoms/cm³. The carrier reservoirs 306 and 307 may have a uniform dopingconcentration or may include sub-regions of different concentrations ordopant profiles. In some embodiments, the carrier reservoirs 306 and 307may have the same doping concentration profile; in other embodiments,the doping concentration profiles of the carrier reservoirs 306 and 307may differ from each other. In some embodiments, the top surface of thesubstrate 302 may be recessed beneath the top surface of an adjacentshallow trench isolation (STI) layer 305, forming a trench 308 in whichthe carrier reservoirs 306 and 307 are disposed. In some embodiments,the carrier reservoirs 306 and 307, and/or the fin 344, may be strained.

The gate dielectric 362 may be disposed between the gate material 366and the fin 344. The gate material 366 and the gate dielectric 362 maybe sacrificial materials (i.e., materials that will be removed andreplaced with alternate materials to form the gate electrode and gatedielectric, respectively, in the IC device) or may themselves be the“final” materials for a gate in the IC device.

A hardmask 337 may be disposed on the gate material 366, and spacers 330may be disposed on opposite faces of the gate material 366/hardmask 337.

In some embodiments, the substrate 302 may include one or more epitaxialsingle crystalline semiconductor layers (e.g., silicon, germanium,silicon germanium, gallium arsenide, indium phosphide, indium galliumarsenide, aluminum gallium arsenide, etc.) grown atop a distinctcrystalline substrate (silicon, germanium, gallium arsenide, sapphire,etc.). In one such embodiment, the epitaxially grown semiconductorlayers may provide one or more buffer layers 309 having latticeconstants different from the distinct crystalline substrate. The bufferlayers 309 may serve to grade the lattice constant from the distinctcrystalline substrate to the top surface. For example, the substrate 302may include epitaxially grown silicon germanium (SiGe) buffer layers 309on a distinct crystalline silicon substrate. The germanium concentrationof the SiGe buffer layers 309 may increase their germanium content fromthe bottom-most buffer layer to the top-most buffer layer (e.g., from30% germanium to 70% germanium), thereby gradually increasing thelattice constant of the substrate 302. In some embodiments, the bufferlayers 309 may have a thickness between 500 nanometers and 3.5 microns.

STI regions 303 may be disposed on the substrate 302. STI regions 303may serve to reduce current leakage between devices formed adjacent toone another. As noted above, an STI layer 305 may be disposed in the STIregions 303. The STI layer 305 may include any appropriate dielectricmaterial, such as silicon oxide, silicon nitride, silicon oxynitride, alow-k dielectric, and any combination thereof. In some embodiments, theSTI layer 305 may itself be a dielectric layer 110, formed in accordancewith any of the protective layer techniques disclosed herein (e.g., asdiscussed above with reference to FIGS. 5-8); in such embodiments, thefin 344 may act as a structure 108.

The fin 344 may be formed from a material that can be reversely alteredfrom an insulating state to a conductive state by applying externalelectric fields. For example, the fin 344 may be formed of Si, Ge, SiGe,GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and/or InP. Insome particular embodiments, the fin 344 may include an undopedlattice-stressed single crystalline semiconductor material having acarrier mobility greater than single crystalline silicon. The absence ofdopants in the fin 344 may reduce scattering of charge carriers and mayhelp to improve carrier mobility and thus increase drive current.Lattice stress in the fin 344 may also enhance carrier mobility andimprove device performance. In some embodiments, the fin 344 may becompressively stressed for enhanced hole mobility in p-type tri-gatetransistors, and may be tensilely stressed for enhanced electronmobility in n-type tri-gate transistors.

The gate dielectric 362 may include any suitable gate dielectric, suchas, but not limited to, SiO2, SiON, and SiN. In some embodiments, thegate dielectric 362 may include a high-k gate dielectric layer, such asa metal oxide dielectric (e.g., Ta2O5, TiO2, HfO2, HfSiOx, ZrO2, etc.).The gate dielectric 362 may also include other types of high-kdielectric layers, such as, but not limited to, lead zirconate titanate(PZT) or barium strontium titanate (BST). The gate dielectric 362 mayinclude any combination of the above dielectric materials; in someembodiments, the gate dielectric 362 may include multiple differentlayers of dielectric materials. In some embodiments, the gate dielectric362 may have a thickness between 30 angstroms and 60 angstroms. In aspecific embodiment, the gate dielectric 362 includes HfO₂ and has athickness between 3 nanometer and 6 nanometers.

The gate material 366 may include any suitable gate electrode material.In some embodiments, the gate material 366 may include a metal such as,but not limited to, Ti, TiN, TaN, W, Ru, TiAl, or any combinationthereof. In some embodiments, the gate material 366 may be formed from amaterial having a work function between 3.9 eV and 4.2 eV. In someembodiments, the gate material 366 may have a work function between 4.8eV and 5.2 eV. In some embodiments in which the fin 344 is undoped orvery lightly doped, the gate material 366 may have a mid-gap workfunction between 4.3 eV and 4.7 eV.

The assembly 216 may be formed by forming the fin 344 on the substrate302 (e.g., by etching the fin 344 from an initial substrate 302),providing the STI layer 305 (e.g., by blanket deposition, planarization,then recess), providing the gate dielectric 362 and the gate material366, providing and patterning the hardmask 337, patterning the gatedielectric 362 and the gate material 366 in accordance with the templateprovided by the patterned hardmask 337, forming the spacers 330 on theside faces of the patterned gate material 366 and hardmask 337, and thenforming the carrier reservoirs 306 and 307.

The pair of sidewall spacers 130 may be formed using conventionalmethods of forming selective spacers, as known in the art. In someembodiments, a conformal dielectric spacer layer, such as, but notlimited to, silicon oxide, silicon nitride, silicon oxynitride, andcombinations thereof, is first blanket-deposited on all structures,including the fin 344. The dielectric spacer layer may be deposited in aconformal manner so that it has substantially equal thicknesses on bothvertical surfaces and horizontal surfaces. The dielectric spacer layermay be deposited using conventional CVD methods such as low-pressurechemical vapor deposition (LPCVD) and plasma-enhanced chemical vapordeposition (PECVD), for example. In some embodiments, the dielectricspacer layer may be deposited to a thickness between 2 nanometers and 10nanometers. Next, an unpatterned anisotropic etch may be performed onthe dielectric spacer layer using conventional anisotropic etch methods,such as reactive ion etching (RIE). During the anisotropic etchingprocess, most of the dielectric spacer layer may be removed fromhorizontal surfaces, leaving the dielectric spacer layer on the verticalsurfaces, as shown. Next, an unpatterned isotropic etch may be performedto remove the remaining dielectric spacer layer from any horizontalsurfaces, leaving pairs of spacers 330. In some embodiments, theisotropic etch is a wet etch process. In a specific embodiment, wherethe dielectric spacer layer is silicon nitride or silicon oxide, theisotropic etch may employ a wet etchant solution comprising phosphoricacid (H₃PO₄) or a buffered oxide etch (BOE), respectively. In analternate embodiment, the isotropic etch may be a dry etch process. Inone such embodiment, nitrogen trifluoride (NF₃) gas may be employed in adownstream plasma reactor to isotropically etch the dielectric spacerlayers. Although the spacers 330 are illustrated as having substantiallyrectangular cross-sections, this is for ease of illustration; in someembodiments, the spacers 330 may be thinner farther from the substrate302 and thicker closer to the substrate 302. In some embodiments, thespacers 330 may have a convex shape, curving outward away from theassociated gate material 366.

FIG. 10 illustrates an assembly 218 subsequent to processing theprotective layer 105 and the initial dielectric material 111 to form adielectric layer 110 over the spacers 330/hardmask 337/gate material 366of the assembly 216 (FIG. 9), in accordance with any of the techniquesdiscussed herein (e.g., with reference to FIGS. 3 and 4), and thenpolishing back the excess dielectric layer 110 and hardmask 337. Theassembly 218 of FIG. 10 is thus an embodiment of the assembly 206 ofFIG. 4. In FIG. 10, the “A” sub-figure represents a cross-sectional viewanalogous to that of FIG. 9A, the “B” sub-figure represents across-sectional view analogous to that of FIG. 9B, the “C” sub-figurerepresents a cross-sectional view analogous to that of FIG. 9C, and the“D” sub-figure represents a top view analogous to that of FIG. 9D. Thepolishing of the excess dielectric layer 110 and removal of the hardmask337 may be achieved by using CMP or any other suitable technique (e.g.,as discussed above with reference to FIG. 7).

The assembly 218 may be further processed to form a tri-gate transistorby, for example, replacing the gate electrode material 366/gatedielectric 362 with other gate electrode material/gate dielectric whenthe gate material 366/gate dielectric 362 are sacrificial (e.g., in areplacement metal gate (RMG) process), and forming interconnects to thegate, source, and drain, among other steps.

FIGS. 11-12 are various views of example stages in the manufacture of anIC device including an all-around gate transistor, in accordance withvarious embodiments. In particular, FIGS. 11-12 illustrate an embodimentin which the protective layer techniques disclosed herein are used toprovide a dielectric layer 110 around spacers 330 that abut the gates ofan all-around gate transistor. As noted above, aggressive dielectricdeposition techniques may damage the spacers 330; use of the protectivelayer techniques disclosed herein may preserve the spacers 330 duringdeposition of the dielectric layer 110.

FIG. 11A is a side cross-sectional view of an assembly 220 along the fin354, FIG. 11B is a cross-sectional view taken through the section A-A ofFIG. 11A, FIG. 11C is a side view taken toward the carrier reservoir306, and FIG. 11D is a top view. The assembly 220 is an embodiment ofthe assembly 204 of FIG. 3; in the assembly 220, the structures 108 areprovided by gate material 366, a hardmask 337, and spacers 330 disposedat opposite faces of the gate material 366/hardmask 337. The base 102 isprovided by a fin 354 on and around which the gate material 366 and thespacers 330 are disposed. The protective layer 105 covers the structure108, and an initial dielectric material 111 is disposed on theprotective layer 105; the protective layer 105 and the initialdielectric material 111 may take the form of any of the embodimentsdisclosed herein.

The assembly 220 may include a substrate 302 on which carrier reservoirs306 and 307 are disposed. The substrate 302, and the carrier reservoirs306 and 307, of the assembly 220 may take any of the forms discussedabove with reference to the assembly 216 (FIG. 9). The carrierreservoirs 306 may provide the source and drain for an all-around gatetransistor formed from the assembly 220, as discussed below.

In the assembly 220, the gate dielectric 362 may be disposed between thegate material 366 and the fin 354, and these materials are sacrificialmaterials (i.e., materials that will be removed and replaced withalternate materials to form the gate electrode and gate dielectric,respectively, in the IC device).

A hardmask 337 may be disposed on the gate material 366, and spacers 330may be disposed on opposite faces of the gate material 366/hardmask 337.The hardmask 337 and the spacers 330 of the assembly 220 may take any ofthe forms discussed above with reference to the assembly 216 (FIG. 9).

STI regions 303 may be disposed on the substrate 302, and an STI layer305 may be disposed in the STI regions 303. The STI layer 305 of theassembly 220 may take any of the forms discussed above with reference tothe assembly 216 (FIG. 9).

The fin 354 may include alternating layers of a semiconductor material360 and a sacrificial material 370. In later processing of the assembly220 to form an all-around gate transistor, portions of the layers ofsacrificial material 370 may be removed and the layers of semiconductormaterial 360 may become nanowires that extend between the carrierreservoirs 306 and 307 and provide the channel of the all-around gatetransistor. As noted above, the gate material 366 and the gatedielectric 362 may be removed prior to removal of the portions of thelayers of sacrificial material, and then new gate dielectric and gatematerial may be deposited so as to surround the nanowires, providing theall-around gates.

The layers of sacrificial material 370 may induce lattice stress on thelayers of semiconductor material 360 by being lattice-mismatched to thelayers of semiconductor material 360. The layers of semiconductormaterial 360 and the layers of sacrificial material 370 may be formedfrom any well-known materials having different lattice constants. Insome embodiments, the layers of semiconductor material 360 and thelayers of sacrificial material 370 are each formed from a singlecrystalline semiconductor material such as, but not limited to, Si, Ge,SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. Insome embodiments, the layers of semiconductor material 360 have alattice constant different from the lattice constants of the layers ofsacrificial material 370 and the top surface of the substrate 302. Thefin 354 may be lattice-stressed as a result of the lattice mismatchbetween the substrate 302, the layers of semiconductor material 360, andthe layers of sacrificial material 370.

The fin 354 may be formed by first blanket depositing alternating layersof semiconductor material 360 and sacrificial material 370 on the topsurface of the substrate 302 using conventional epitaxial chemical vapordeposition (CVD) methods. Next, the blanket layers of semiconductormaterial 360 and sacrificial material 370 may be patterned usingconventional photolithography and etching methods to define the fin 354.In some embodiments, the substrate 302 may also be etched so that abottom portion of the fin 354 includes a portion of the substrate 302(e.g., a portion of the buffer layers 309). In this way, the portion ofthe substrate 302 that is included in the fin 354 may act as the bottomsacrificial material 370 of the fin 354.

The assembly 220 may be formed by forming the fin 354 on the substrate302 (e.g., as discussed above), providing the STI layer 305 (e.g., byblanket deposition, planarization, then recess), providing the gatedielectric 362 and the gate material 366, providing and patterning thehardmask 337, patterning the gate dielectric 362 and the gate material366 in accordance with the template provided by the patterned hardmask337, forming the spacers 330 on the side faces of the patterned gateelectrode material 366 and hardmask 337, and then forming the carrierreservoirs 306 and 307.

FIG. 12 illustrates an assembly 222 subsequent to processing theprotective layer 105 and the initial dielectric material 111 to form adielectric layer 110 over the spacers 330/hardmask 337/gate material 366of the assembly 220 (FIG. 11), in accordance with any of the techniquesdiscussed herein (e.g., with reference to FIGS. 3 and 4), and thenpolishing back the excess dielectric layer 110 and hardmask 337. Theassembly 222 of FIG. 12 is thus an embodiment of the assembly 206 ofFIG. 4. In FIG. 12, the “A” sub-figure represents a cross-sectional viewanalogous to that of FIG. 11A, the “B” sub-figure represents across-sectional view analogous to that of FIG. 11B, the “C” sub-figurerepresents a cross-sectional view analogous to that of FIG. 11C, and the“D” sub-figure represents a top view analogous to that of FIG. 11D. Thepolishing of the excess dielectric layer 110 and removal of the hardmask337 of the assembly 220 may be achieved by using CMP or any othersuitable technique (e.g., as discussed above with reference to FIG. 7).

As noted above, the assembly 222 may be further processed to form anall-around gate transistor by, for example, removing the sacrificialgate material 366/gate dielectric 362, removing the exposed sacrificialmaterial 370, providing gate dielectric and gate material on the exposedsemiconductor material 360, and forming interconnects to the gate,source, and drain, among other steps.

FIG. 13 is a flow diagram illustrating a method 1000 for forming adielectric layer 110, in accordance various embodiments. Although thevarious operations discussed with reference to the method 1000 are shownin a particular order and once each, the operations may be performed inany suitable order (e.g., in any combination of parallel or seriesperformance), and may be repeated or omitted as suitable. Additionally,although various operations of the method 1000 may be illustrated withreference to particular materials disclosed herein, these are simplyexamples, and the method 1000 may be used with any suitable materials.

At 1002, a protective layer may be provided on an assembly. In someembodiments, the protective layer may be a conformal layer. In someembodiments, the protective layer may fill high aspect ratio recesses inthe assembly. For example, the protective layer of 1002 may take any ofthe forms discussed herein with reference to the protective layer 105.

At 1004, an initial dielectric material may be provided on theprotective layer so that the protective layer is disposed between theinitial dielectric material and the assembly. In some embodiments, theinitial dielectric material may be provided by FCVD. For example, theinitial dielectric material of 1004 may take any of the forms discussedherein with reference to the initial dielectric material 111.

At 1006, the protective layer and initial dielectric material may betreated to convert the protective layer and initial dielectric materialinto a dielectric layer. In some embodiments, the dielectric layer mayhave a substantially homogenous material composition. For example, anyof the curing and/or post-treatments disclosed herein may be performed,as suitable, to form any of the dielectric layers 110 disclosed herein.

Dielectric layers 110 formed using the protective layer techniquesdisclosed herein may be included in any suitable electronic device.FIGS. 14-17 illustrate various examples of apparatuses that may includedielectric layers formed using any of the protective layer techniquesdisclosed herein.

FIGS. 14A-14B are top views of a wafer 5200 and dies 5202 that mayinclude dielectric layers formed using any of the protective layertechniques disclosed herein. The wafer 5200 may be composed ofsemiconductor material and may include one or more dies 5202 having ICelements formed on a surface of the wafer 5200. Each of the dies 5202may be a repeating unit of a semiconductor product that includes anysuitable IC. After the fabrication of the semiconductor product iscomplete, the wafer 5200 may undergo a singulation process in which eachof the dies 5202 is separated from one another to provide discrete“chips” of the semiconductor product. The die 5202 may include one ormore transistors (e.g., some of the transistors 5340 of FIG. 15,discussed below), supporting circuitry to route electrical signals tothe transistors, insulating material (e.g., dielectric layers formedusing any of the protective layer techniques), as well as any other ICcomponents. In some embodiments, the wafer 5200 or the die 5202 mayinclude a memory device (e.g., a static random access memory (SRAM)device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any othersuitable circuit element. Multiple ones of these devices may be combinedon a single die 5202. For example, a memory array formed by multiplememory devices may be formed on a same die 5202 as a processing device(e.g., the processing device 5502 of FIG. 17) or other logic that isconfigured to store information in the memory devices or executeinstructions stored in the memory array. In some embodiments, the die5202 may include fins isolated from each other by a dielectric layerformed using any of the protective layer techniques, or transistor gatesisolated by a dielectric layer formed using any of the protective layertechniques.

FIG. 15 is a cross-sectional side view of an IC device 5300 that mayinclude dielectric layers formed using any of the protective layertechniques disclosed herein. For example, any of the insulating materialincluded in the IC device 5300 may be formed using the protective layertechniques disclosed herein.

The IC device 5300 may be formed on a substrate 5302 (e.g., the wafer5200 of FIG. 14A) and may be included in a die (e.g., the die 5202 ofFIG. 14B). The substrate 5302 may be a semiconductor substrate composedof semiconductor material systems including, for example, N-type orP-type material systems. The substrate 5302 may include, for example, acrystalline substrate formed using a bulk silicon or asilicon-on-insulator substructure. In some embodiments, the substrate5302 may be formed using alternative materials, which may or may not becombined with silicon, that include but are not limited to germanium,indium antimonide, lead telluride, indium arsenide, indium phosphide,gallium arsenide, or gallium antimonide. Further materials classified asgroup II-VI, III-V, or IV may also be used to form the substrate 5302.Although a few examples of materials from which the substrate 5302 maybe formed are described here, any material that may serve as afoundation for an IC device 5300 may be used. The substrate 5302 may bepart of a singulated die (e.g., the dies 5202 of FIG. 14B) or a wafer(e.g., the wafer 5200 of FIG. 14A).

The IC device 5300 may include one or more device layers 5304 disposedon the substrate 5302. The device layer 5304 may include features of oneor more transistors 5340 (e.g., metal oxide semiconductor field-effecttransistors (MOSFETs)) formed on the substrate 5302. The device layer5304 may include, for example, one or more source and/or drain (S/D)regions 5320, a gate 5322 to control current flow in the transistors5340 between the S/D regions 5320, and one or more S/D contacts 5324 toroute electrical signals to/from the S/D regions 5320. The transistors5340 may include additional features not depicted for the sake ofclarity, such as device isolation regions, gate contacts, and the like.The transistors 5340 are not limited to the type and configurationdepicted in FIG. 15 and may include a wide variety of other types andconfigurations such as, for example, planar transistors, nonplanartransistors, or a combination of both. Nonplanar transistors may includeFinFET transistors, such as double-gate transistors or tri-gatetransistors, and wraparound or all-around gate transistors, such asnanoribbon and nanowire transistors. For example, the transistors 5340may include tri-gate transistors formed as discussed above withreference to FIGS. 9-10, or all-around gate transistors formed asdiscussed above with reference to FIGS. 11-12.

Each transistor 5340 may include a gate 5322 formed of at least twolayers, a gate dielectric layer and a gate electrode layer. The gatedielectric layer may include one layer or a stack of layers. The one ormore layers may include silicon oxide, silicon dioxide, and/or a high-kdielectric material. The high-k dielectric material may include elementssuch as hafnium, silicon, oxygen, titanium, tantalum, lanthanum,aluminum, zirconium, barium, strontium, yttrium, lead, scandium,niobium, and zinc. Examples of high-k materials that may be used in thegate dielectric layer include, but are not limited to, hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. In some embodiments, an annealing processmay be carried out on the gate dielectric layer to improve its qualitywhen a high-k material is used.

The gate electrode layer may be formed on the gate dielectric layer andmay include at least one P-type work-function metal or N-typework-function metal, depending on whether the transistor 5340 is to be aPMOS or an NMOS transistor. In some implementations, the gate electrodelayer may consist of a stack of two or more metal layers, where one ormore metal layers are work-function metal layers and at least one metallayer is a fill metal layer. Further metal layers may be included forother purposes, such as a barrier layer. For a PMOS transistor, metalsthat may be used for the gate electrode include, but are not limited to,ruthenium, palladium, platinum, cobalt, nickel, and conductive metaloxides (e.g., ruthenium oxide). For an NMOS transistor, metals that maybe used for the gate electrode include, but are not limited to, hafnium,zirconium, titanium, tantalum, aluminum, alloys of these metals, andcarbides of these metals (e.g., hafnium carbide, zirconium carbide,titanium carbide, tantalum carbide, and aluminum carbide).

In some embodiments, when viewed as a cross section of the transistor5340 along the source-channel-drain direction, the gate electrode mayconsist of a U-shaped structure that includes a bottom portionsubstantially parallel to the surface of the substrate and two sidewallportions that are substantially perpendicular to the top surface of thesubstrate. In other embodiments, at least one of the metal layers thatform the gate electrode may simply be a planar layer that issubstantially parallel to the top surface of the substrate and does notinclude sidewall portions substantially perpendicular to the top surfaceof the substrate. In other embodiments, the gate electrode may consistof a combination of U-shaped structures and planar, non-U-shapedstructures. For example, the gate electrode may consist of one or moreU-shaped metal layers formed atop one or more planar, non-U-shapedlayers.

In some embodiments, a pair of sidewall spacers may be formed onopposing sides of the gate stack to bracket the gate stack. The sidewallspacers may be formed from a material such as silicon nitride, siliconoxide, silicon carbide, silicon nitride doped with carbon, and siliconoxynitride. Processes for forming sidewall spacers are well known in theart and generally include deposition and etching process steps. In someembodiments, a plurality of spacer pairs may be used; for instance, twopairs, three pairs, or four pairs of sidewall spacers may be formed onopposing sides of the gate stack. In some embodiments, as discussedabove with reference to FIGS. 9-12, the dielectric material abutting thesidewall spacers may be formed using any of the protective layertechniques disclosed herein.

The S/D regions 5320 may be formed within the substrate 5302 adjacent tothe gate 5322 of each transistor 5340. The S/D regions 5320 may beformed using either an implantation/diffusion process or anetching/deposition process, for example. In the former process, dopantssuch as boron, aluminum, antimony, phosphorous, or arsenic may beion-implanted into the substrate 5302 to form the S/D regions 5320. Anannealing process that activates the dopants and causes them to diffusefarther into the substrate 5302 may follow the ion-implantation process.In the latter process, the substrate 5302 may first be etched to formrecesses at the locations of the S/D regions 5320. An epitaxialdeposition process may then be carried out to fill the recesses withmaterial that is used to fabricate the S/D regions 5320. In someimplementations, the S/D regions 5320 may be fabricated using a siliconalloy such as silicon germanium or silicon carbide. In some embodiments,the epitaxially deposited silicon alloy may be doped in situ withdopants such as boron, arsenic, or phosphorous. In some embodiments, theS/D regions 5320 may be formed using one or more alternate semiconductormaterials such as germanium or a group III-V material or alloy. Infurther embodiments, one or more layers of metal and/or metal alloys maybe used to form the S/D regions 5320. Particular examples ofsource/drain formation techniques are also discussed above withreference to FIGS. 9-10.

Although the transistors 5340 are illustrated in FIG. 15 as located in asingle device layer 5304, in some embodiments, transistors 5340 may belocated in additional layers in the interlayer dielectric (ILD) stack5319 of the IC device 5300. In particular, one or more interconnectlayers may be disposed between the device layer 5304 and one or moreadditional layers (not shown) including one or more transistors of anyof the types disclosed herein.

Electrical signals, such as power and/or input/output (I/O) signals, maybe routed to and/or from the transistors 5340 of the device layer 5304through one or more interconnect layers disposed on the device layer5304 (illustrated in FIG. 15 as interconnect layers 5306-5310). Forexample, electrically conductive features of the device layer 5304(e.g., the gate 5322 and the S/D contacts 5324) may be electricallycoupled with the interconnect structures 5328 of the interconnect layers5306-5310. The one or more interconnect layers 5306-5310 may form theILD stack 5319 of the IC device 5300.

The interconnect structures 5328 may be arranged within the interconnectlayers 5306-5310 to route electrical signals according to a wide varietyof designs (in particular, the arrangement is not limited to theparticular configuration of interconnect structures 5328 depicted inFIG. 15). Although a particular number of interconnect layers 5306-5310is depicted in FIG. 15, embodiments of the present disclosure include ICdevices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 5328 may includeconductive lines 5328 a and/or conductive vias 5328 b filled with anelectrically conductive material such as a metal. The conductive lines5328 a may be arranged to route electrical signals in a direction of aplane that is substantially parallel with a surface of the substrate5302 upon which the device layer 5304 is formed. For example, theconductive lines 5328 a may route electrical signals in a direction inand out of the page from the perspective of FIG. 15. The conductive vias5328 b may be arranged to route electrical signals in a direction of aplane that is substantially perpendicular to the surface of thesubstrate 5302 upon which the device layer 5304 is formed.

The interconnect layers 5306-5310 may include a dielectric material 5326disposed between the interconnect structures 5328, as shown in FIG. 15.In some embodiments, the dielectric material 5326 disposed between theinterconnect structures 5328 in different ones of the interconnectlayers 5306-5310 may have different compositions; in other embodiments,the composition of the dielectric material 5326 between differentinterconnect layers 5306-5310 may be the same. In some embodiments, someor all of the dielectric material 5326 may take the form of thedielectric layer 110, and may be formed using any of the protectivelayer techniques disclosed herein.

A first interconnect layer 5306 (referred to as Metal 1 or “M1”) may beformed directly on the device layer 5304. In some embodiments, the firstinterconnect layer 5306 may include conductive lines 5328 a and/orconductive vias 5328 b, as shown. The conductive lines 5328 a of thefirst interconnect layer 5306 may be coupled with contacts (e.g., theS/D contacts 5324) of the device layer 5304.

A second interconnect layer 5308 (referred to as Metal 2 or “M2”) may beformed directly on the first interconnect layer 5306. In someembodiments, the second interconnect layer 5308 may include conductivevias 5328 b to couple the conductive lines 5328 a of the secondinterconnect layer 5308 with the conductive lines 5328 a of the firstinterconnect layer 5306. Although the conductive lines 5328 a and theconductive vias 5328 b are structurally delineated with a line withineach interconnect layer (e.g., within the second interconnect layer5308) for the sake of clarity, the conductive lines 5328 a and theconductive vias 5328 b may be structurally and/or materially contiguous(e.g., simultaneously filled during a dual-damascene process) in someembodiments.

A third interconnect layer 5310 (referred to as Metal 3 or “M3”) (andadditional interconnect layers, as desired) may be formed in successionon the second interconnect layer 5308 according to similar techniquesand configurations described in connection with the second interconnectlayer 5308 or the first interconnect layer 5306.

The IC device 5300 may include a solder resist material 5334 (e.g.,polyimide or similar material) and one or more bond pads 5336 formed onthe interconnect layers 5306-5310. The bond pads 5336 may beelectrically coupled with the interconnect structures 5328 andconfigured to route the electrical signals of the transistor(s) 5340 toother external devices. For example, solder bonds may be formed on theone or more bond pads 5336 to mechanically and/or electrically couple achip including the IC device 5300 with another component (e.g., acircuit board). The IC device 5300 may have other alternativeconfigurations to route the electrical signals from the interconnectlayers 5306-5310 than depicted in other embodiments. For example, thebond pads 5336 may be replaced by or may further include other analogousfeatures (e.g., posts) that route the electrical signals to externalcomponents.

FIG. 16 is a cross-sectional side view of an IC device assembly 5400that may include dielectric layers formed using any of the protectivelayer techniques disclosed herein. The IC device assembly 5400 includesa number of components disposed on a circuit board 5402. The IC deviceassembly 5400 may include components disposed on a first face 5440 ofthe circuit board 5402 and an opposing second face 5442 of the circuitboard 5402; generally, components may be disposed on one or both faces5440 and 5442.

In some embodiments, the circuit board 5402 may be a printed circuitboard (PCB) including multiple metal layers separated from one anotherby layers of dielectric material and interconnected by electricallyconductive vias. Any one or more of the metal layers may be formed in adesired circuit pattern to route electrical signals (optionally inconjunction with other metal layers) between the components coupled tothe circuit board 5402. In other embodiments, the circuit board 5402 maybe a non-PCB substrate.

The IC device assembly 5400 illustrated in FIG. 16 includes apackage-on-interposer structure 5436 coupled to the first face 5440 ofthe circuit board 5402 by coupling components 5416. The couplingcomponents 5416 may electrically and mechanically couple thepackage-on-interposer structure 5436 to the circuit board 5402, and mayinclude solder balls (as shown in FIG. 16), male and female portions ofa socket, an adhesive, an underfill material, and/or any other suitableelectrical and/or mechanical coupling structure.

The package-on-interposer structure 5436 may include an IC package 5420coupled to an interposer 5404 by coupling components 5418. The couplingcomponents 5418 may take any suitable form for the application, such asthe forms discussed above with reference to the coupling components5416. Although a single IC package 5420 is shown in FIG. 16, multiple ICpackages may be coupled to the interposer 5404; indeed, additionalinterposers may be coupled to the interposer 5404. The interposer 5404may provide an intervening substrate used to bridge the circuit board5402 and the IC package 5420. The IC package 5420 may be or include, forexample, a die (the die 5202 of FIG. 14B), an IC device (e.g., the ICdevice 5300 of FIG. 15 or any of the devices disclosed herein), or anyother suitable component. Generally, the interposer 5404 may spread aconnection to a wider pitch or reroute a connection to a differentconnection. For example, the interposer 5404 may couple the IC package5420 (e.g., a die) to a ball grid array (BGA) of the coupling components5416 for coupling to the circuit board 5402. In the embodimentillustrated in FIG. 16, the IC package 5420 and the circuit board 5402are attached to opposing sides of the interposer 5404; in otherembodiments, the IC package 5420 and the circuit board 5402 may beattached to a same side of the interposer 5404. In some embodiments,three or more components may be interconnected by way of the interposer5404.

The interposer 5404 may be formed of an epoxy resin, afiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In some embodiments, the interposer 5404 maybe formed of alternate rigid or flexible materials that may include thesame materials described above for use in a semiconductor substrate,such as silicon, germanium, and other group III-V and group IVmaterials. The interposer 5404 may include metal interconnects 5408 andvias 5410, including but not limited to through-silicon vias (TSVs)5406. The interposer 5404 may further include embedded devices 5414,including both passive and active devices. Such devices may include, butare not limited to, capacitors, decoupling capacitors, resistors,inductors, fuses, diodes, transformers, sensors, electrostatic discharge(ESD) devices, and memory devices. More complex devices such asradio-frequency (RF) devices, power amplifiers, power managementdevices, antennas, arrays, sensors, and microelectromechanical systems(MEMS) devices may also be formed on the interposer 5404. Thepackage-on-interposer structure 5436 may take the form of any of thepackage-on-interposer structures known in the art.

The IC device assembly 5400 may include an IC package 5424 coupled tothe first face 5440 of the circuit board 5402 by coupling components5422. The coupling components 5422 may take the form of any of theembodiments discussed above with reference to the coupling components5416, and the IC package 5424 may take the form of any of theembodiments discussed above with reference to the IC package 5420.

The IC device assembly 5400 illustrated in FIG. 16 includes apackage-on-package structure 5434 coupled to the second face 5442 of thecircuit board 5402 by coupling components 5428. The package-on-packagestructure 5434 may include an IC package 5426 and an IC package 5432coupled together by coupling components 5430 such that the IC package5426 is disposed between the circuit board 5402 and the IC package 5432.The coupling components 5428 and 5430 may take the form of any of theembodiments of the coupling components 5416 discussed above, and the ICpackages 5426 and 5432 may take the form of any of the embodiments ofthe IC package 5420 discussed above.

FIG. 17 is a block diagram of an example computing device 5500 that mayinclude dielectric layers formed using any of the protective layertechniques disclosed herein. For example, any suitable ones of thecomponents of the computing device 5500 may include, or be included in,a die including dielectric layers formed using any of the protectivelayer techniques disclosed herein. A number of components areillustrated in FIG. 17 as included in the computing device 5500, but anyone or more of these components may be omitted or duplicated, assuitable for the application. In some embodiments, some or all of thecomponents included in the computing device 5500 may be attached to oneor more motherboards. In some embodiments, some or all of thesecomponents are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device 5500 may notinclude one or more of the components illustrated in FIG. 17, but thecomputing device 5500 may include interface circuitry for coupling tothe one or more components. For example, the computing device 5500 maynot include a display device 5506, but may include display deviceinterface circuitry (e.g., a connector and driver circuitry) to which adisplay device 5506 may be coupled. In another set of examples, thecomputing device 5500 may not include an audio input device 5524 or anaudio output device 5508, but may include audio input or output deviceinterface circuitry (e.g., connectors and supporting circuitry) to whichan audio input device 5524 or audio output device 5508 may be coupled.

The computing device 5500 may include a processing device 5502 (e.g.,one or more processing devices). As used herein, the term “processingdevice” or “processor” may refer to any device or portion of a devicethat processes electronic data from registers and/or memory to transformthat electronic data into other electronic data that may be stored inregisters and/or memory. The processing device 5502 may include one ormore digital signal processors (DSPs), application-specific integratedcircuits (ASICs), central processing units (CPUs), graphics processingunits (GPUs), cryptoprocessors (specialized processors that executecryptographic algorithms within hardware), server processors, or anyother suitable processing devices. The computing device 5500 may includea memory 5504, which may itself include one or more memory devices suchas volatile memory (e.g., dynamic random access memory (DRAM)),nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solidstate memory, and/or a hard drive. In some embodiments, the memory 5504may include memory that shares a die with the processing device 5502.This memory may be used as cache memory and may include embedded dynamicrandom access memory (eDRAM) or spin transfer torque magneticrandom-access memory (STT-MRAM). In some embodiments, the processingdevice 5502 and/or the memory 5504 may include dielectric layers formedusing any of the protective layer techniques disclosed herein.

In some embodiments, the computing device 5500 may include acommunication chip 5512 (e.g., one or more communication chips). Forexample, the communication chip 5512 may be configured for managingwireless communications for the transfer of data to and from thecomputing device 5500. The term “wireless” and its derivatives may beused to describe circuits, devices, systems, methods, techniques,communications channels, etc., that may communicate data through the useof modulated electromagnetic radiation through a nonsolid medium. Theterm does not imply that the associated devices do not contain anywires, although in some embodiments they might not. In some embodiments,the communication chip 5512 may include dielectric layers formed usingany of the protective layer techniques disclosed herein.

The communication chip 5512 may implement any of a number of wirelessstandards or protocols, including but not limited to Institute forElectrical and Electronic Engineers (IEEE) standards including Wi-Fi(IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005Amendment), Long-Term Evolution (LTE) project along with any amendments,updates, and/or revisions (e.g., advanced LTE project, ultra-mobilebroadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE802.16 compatible Broadband Wireless Access (BWA) networks are generallyreferred to as WiMAX networks, an acronym that stands for WorldwideInteroperability for Microwave Access, which is a certification mark forproducts that pass conformity and interoperability tests for the IEEE802.16 standards. The communication chip 5512 may operate in accordancewith a Global System for Mobile Communication (GSM), General PacketRadio Service (GPRS), Universal Mobile Telecommunications System (UMTS),High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communication chip 5512 may operate in accordance with Enhanced Datafor GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN),Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN(E-UTRAN). The communication chip 5512 may operate in accordance withCode Division Multiple Access (CDMA), Time Division Multiple Access(TDMA), Digital Enhanced Cordless Telecommunications (DECT),Evolution-Data Optimized (EV-DO), and derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The communication chip 5512 may operate in accordance with otherwireless protocols in other embodiments. The computing device 5500 mayinclude an antenna 5522 to facilitate wireless communications and/or toreceive other wireless communications (such as AM or FM radiotransmissions).

In some embodiments, the communication chip 5512 may manage wiredcommunications, such as electrical, optical, or any other suitablecommunication protocols (e.g., the Ethernet). As noted above, thecommunication chip 5512 may include multiple communication chips. Forinstance, a first communication chip 5512 may be dedicated toshorter-range wireless communications such as Wi-Fi or Bluetooth, and asecond communication chip 5512 may be dedicated to longer-range wirelesscommunications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, orothers. In some embodiments, a first communication chip 5512 may bededicated to wireless communications, and a second communication chip5512 may be dedicated to wired communications.

The computing device 5500 may include battery/power circuitry 5514. Thebattery/power circuitry 5514 may include one or more energy storagedevices (e.g., batteries or capacitors) and/or circuitry for couplingcomponents of the computing device 5500 to an energy source separatefrom the computing device 5500 (e.g., AC line power).

The computing device 5500 may include a display device 5506 (orcorresponding interface circuitry, as discussed above). The displaydevice 5506 may include any visual indicators, such as a heads-updisplay, a computer monitor, a projector, a touchscreen display, aliquid crystal display (LCD), a light-emitting diode display, or a flatpanel display, for example.

The computing device 5500 may include an audio output device 5508 (orcorresponding interface circuitry, as discussed above). The audio outputdevice 5508 may include any device that generates an audible indicator,such as speakers, headsets, or earbuds, for example.

The computing device 5500 may include an audio input device 5524 (orcorresponding interface circuitry, as discussed above). The audio inputdevice 5524 may include any device that generates a signalrepresentative of a sound, such as microphones, microphone arrays, ordigital instruments (e.g., instruments having a musical instrumentdigital interface (MIDI) output).

The computing device 5500 may include a global positioning system (GPS)device 5518 (or corresponding interface circuitry, as discussed above).The GPS device 5518 may be in communication with a satellite-basedsystem and may receive a location of the computing device 5500, as knownin the art.

The computing device 5500 may include another output device 5510 (orcorresponding interface circuitry, as discussed above). Examples of theother output device 5510 may include an audio codec, a video codec, aprinter, a wired or wireless transmitter for providing information toother devices, or an additional storage device.

The computing device 5500 may include another input device 5520 (orcorresponding interface circuitry, as discussed above). Examples of theother input device 5520 may include an accelerometer, a gyroscope, acompass, an image capture device, a keyboard, a cursor control devicesuch as a mouse, a stylus, a touchpad, a bar code reader, a QuickResponse (QR) code reader, any sensor, or a radio frequencyidentification (RFID) reader.

The computing device 5500 may have any desired form factor, such as ahand-held or mobile computing device (e.g., a cell phone, a smart phone,a mobile internet device, a music player, a tablet computer, a laptopcomputer, a netbook computer, an ultrabook computer, a personal digitalassistant (PDA), an ultra-mobile personal computer, etc.), a desktopcomputing device, a server or other networked computing component, aprinter, a scanner, a monitor, a set-top box, an entertainment controlunit, a vehicle control unit, a digital camera, a digital videorecorder, or a wearable computing device. In some embodiments, thecomputing device 5500 may be any other electronic device that processesdata.

The following paragraphs provide various examples of the embodimentsdisclosed herein.

Example 1 is an integrated circuit (IC) device, including: a firststructure on a base, wherein the first structure has a width that is 4nanometers or less; a second structure on the base, wherein the secondstructure has a width that is 4 nanometers or less; a trench bounded bythe first structure, the second structure, and the base, wherein thetrench has a height-to-width aspect ratio greater than or equal to 4:1;and a dielectric layer that fills at least a bottom portion of thetrench.

Example 2 may include the subject matter of Example 1, and may furtherspecify that the first structure is a first fin and the second structureis a second fin.

Example 3 may include the subject matter of Example 2, and may furtherspecify that the first fin is a semiconductor fin, the second fin is asemiconductor fin, and the first fin, the second fin, and the base havethe same semiconductor composition.

Example 4 may include the subject matter of Example 2, and may furtherspecify that the first fin includes multiple different material layers,and the second fin includes multiple different material layers.

Example 5 may include the subject matter of any of Examples 2-4, and mayfurther include: a first gate on the first fin; and a second gate on thesecond fin.

Example 6 may include the subject matter of any of Examples 1-5, and mayfurther specify that the trench has a width of 30 nanometers or less.

Example 7 may include the subject matter of any of Examples 1-6, and mayfurther specify that the dielectric layer includes an oxide, a nitride,or a carbide.

Example 8 may include the subject matter of any of Examples 1-7, and mayfurther specify that the dielectric layer has a homogenous composition.

Example 9 may include the subject matter of any of Examples 1-8, and mayfurther specify that the dielectric layer includes a first dielectricportion that is conformal over the first structure and the secondstructure, and a second dielectric portion on the first dielectricportion.

Example 10 may include the subject matter of Example 9, and may furtherspecify that the first dielectric portion and the second dielectricportion have different material compositions.

Example 11 is a method of manufacturing an integrated circuit (IC)device, including: providing a first dielectric material on a structure;providing a second dielectric material on the first dielectric material,wherein the first dielectric material and the second dielectric materialhave different material compositions; and annealing the first dielectricmaterial and the second dielectric material.

Example 12 may include the subject matter of Example 11, and may furtherspecify that providing the first dielectric material includesconformally depositing the first dielectric material.

Example 13 may include the subject matter of Example 12, and may furtherspecify that conformally depositing the first dielectric materialincludes depositing the first dielectric material via atomic layerdeposition (ALD).

Example 14 may include the subject matter of any of Examples 11-13,wherein providing the second dielectric material includes providing aflowable dielectric material.

Example 15 may include the subject matter of Example 14, and may furtherspecify that providing the flowable dielectric material includes using aflowable chemical vapor deposition (FCVD) process.

Example 16 may include the subject matter of any of Examples 14-15, andmay further specify that providing the second dielectric materialincludes curing the flowable dielectric material.

Example 17 may include the subject matter of any of Examples 11-16, andmay further specify that annealing the first dielectric material and thesecond dielectric material results in converting the first dielectricmaterial and the second dielectric material into a substantiallymaterially homogenous dielectric layer.

Example 18 may include the subject matter of any of Examples 11-17, andmay further specify that the first dielectric material includes anoxide, a carbide, or a nitride.

Example 19 may include the subject matter of any of Examples 11-18, andmay further specify that annealing the first dielectric material and thesecond dielectric material includes performing a plasma anneal.

Example 20 may include the subject matter of any of Examples 11-19, andmay further specify that the structure includes sidewall spacers.

Example 21 may include the subject matter of any of Examples 11-20, andmay further specify that the structure includes a fin.

Example 22 is a computing device, including: a processing deviceincluding a first transistor and a second transistor, wherein the firsttransistor includes at least a portion of a first fin, the first fin hasa width that is 4 nanometers or less, the second transistor includes atleast a portion of a second fin, the second fin has a width that is 4nanometers or less, the first transistor and the second transistordefine a trench therebetween, the trench has a height-to-width aspectratio greater than or equal to 4:1, and a dielectric layer fills atleast a bottom portion of the trench; and a memory device,communicatively coupled to the processing device.

Example 23 may include the subject matter of Example 22, and may furtherspecify that the first fin and the second fin extend from asemiconductor substrate.

Example 24 may include the subject matter of Example 22, and may furtherspecify that the first fin and the second fin are spaced apart from asemiconductor substrate by one or more intervening interconnect layers.

Example 25 may include the subject matter of any of Examples 22-24, andmay further specify that the computing device further includes acommunication chip.

1. An integrated circuit (IC) device, comprising: a first structure on abase, wherein the first structure has a width that is 4 nanometers orless; a second structure on the base, wherein the second structure has awidth that is 4 nanometers or less; a trench bounded by the firststructure, the second structure, and the base, wherein the trench has aheight-to-width aspect ratio greater than or equal to 4:1; and adielectric layer that fills at least a bottom portion of the trench. 2.The IC device of claim 1, wherein the first structure is a first fin andthe second structure is a second fin.
 3. The IC device of claim 2,wherein the first fin is a semiconductor fin, the second fin is asemiconductor fin, and the first fin, the second fin, and the base havea same semiconductor composition.
 4. The IC device of claim 2, whereinthe first fin includes multiple different material layers, and thesecond fin includes multiple different material layers.
 5. The IC deviceof claim 2, further comprising: a first gate on the first fin; and asecond gate on the second fin.
 6. The IC device of claim 5, furthercomprising a pair of spacers abutting the first gate, the pair ofspacers separating the first gate from the dielectric layer.
 7. The ICdevice of claim 1, wherein the trench has a width of 30 nanometers orless.
 8. The IC device of claim 1, wherein the dielectric layer includesan oxide, a nitride, or a carbide.
 9. The IC device of claim 1, whereinthe dielectric layer includes a first dielectric portion that isconformal over the first structure and the second structure, and asecond dielectric portion on the first dielectric portion.
 10. The ICdevice of claim 9, wherein the first dielectric portion and the seconddielectric portion have different material compositions.
 11. The ICdevice of claim 9, wherein the first dielectric portion has a thicknessbetween 1 nanometer and 4 nanometers.
 12. The IC device of claim 1,wherein the dielectric layer fills a bottom portion of the trench, and aportion of the first structure and a portion of the second structureextend above a top of the dielectric layer.
 13. A computing device,comprising: a processing device including a first transistor and asecond transistor, wherein the first transistor includes at least aportion of a first fin, the first fin has a width that is 4 nanometersor less, the second transistor includes at least a portion of a secondfin, the second fin has a width that is 4 nanometers or less, the firsttransistor and the second transistor define a trench therebetween, thetrench has a height-to-width aspect ratio greater than or equal to 4:1,and a dielectric layer fills at least a bottom portion of the trench;and a memory device, communicatively coupled to the processing device.14. The computing device of claim 13, wherein the first fin and thesecond fin extend from a semiconductor substrate.
 15. The computingdevice of claim 14, wherein the first fin is a semiconductor fin, thesecond fin is a semiconductor fin, and the first fin, the second fin,and the base have a same semiconductor composition.
 16. The computingdevice of claim 13, further comprising: a first gate on the first fin;and a second gate on the second fin.
 17. The computing device of claim16, further comprising a pair of spacers abutting the first gate, thepair of spacers separating the first gate from the dielectric layer. 18.The computing device of claim 13, wherein the dielectric layer includesa first dielectric portion that is conformal over the first fin and thesecond fin, and a second dielectric portion on the first dielectricportion.
 19. The computing device of claim 18, wherein the firstdielectric portion and the second dielectric portion have differentmaterial compositions.
 20. The computing device of claim 18, wherein thefirst dielectric portion has a thickness between 1 nanometer and 4nanometers.